INTCLR=0, TNEARIEN=0, RNFULLIEN=0, RNFULLF_MARK=0, TNEAREF_MARK=0, FIFOMODE=0
SPI control register 3
| FIFOMODE | FIFO mode enable 0 (0): Buffer mode disabled 1 (1): Data available in the receive data buffer |
| RNFULLIEN | Receive FIFO nearly full interrupt enable 0 (0): No interrupt upon RNFULLF being set 1 (1): Enable interrupts upon RNFULLF being set |
| TNEARIEN | Transmit FIFO nearly empty interrupt enable 0 (0): No interrupt upon TNEAREF being set 1 (1): Enable interrupts upon TNEAREF being set |
| INTCLR | Interrupt clearing mechanism select 0 (0): These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs 1 (1): These interrupts are cleared by writing the corresponding bits in the CI register |
| RNFULLF_MARK | Receive FIFO nearly full watermark 0 (0): RNFULLF is set when the receive FIFO has 48 bits or more 1 (1): RNFULLF is set when the receive FIFO has 32 bits or more |
| TNEAREF_MARK | Transmit FIFO nearly empty watermark 0 (0): TNEAREF is set when the transmit FIFO has 16 bits or less 1 (1): TNEAREF is set when the transmit FIFO has 32 bits or less |